This cutting-edge new volume covers the hardware architecture implementation, the software implementation approach, and the efficient hardware of machine learning applications with FPGA or CMOS circuits, and many other aspects and applications of machine learning techniques for VLSI chip design.
Table of ContentsList of Contributors
Preface
1. Applications of VLSI Design in Artificial Intelligence and Machine LearningImran Ullah Khan, Nupur Mittal and Mohd. Amir Ansari
1.1 Introduction
1.2 Artificial Intelligence
1.3 Artificial Intelligence & VLSI (AI and VLSI)
1.4 Applications of AI
1.5 Machine Learning
1.6 Applications of ML
1.6.1 Role of ML in Manufacturing Process
1.6.2 Reducing Maintenance Costs and Improving Reliability
1.6.3 Enhancing New Design
1.7 Role of ML in Mask Synthesis
1.8 Applications in Physical Design
1.8.1 Lithography Hotspot Detection
1.8.2 Pattern Matching Approach
1.9 Improving Analysis Correlation
1.10 Role of ML in Data Path Placement
1.11 Role of ML on Route Ability Prediction
1.12 Conclusion
References
2. Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine LearningA.V. Ananthalakshmi, P. Divyaparameswari and P. Kanimozhi
2.1 Introduction
2.2 Methods and Methodology
2.2.1 Design of an n-Bit Squaring Circuit Based on (n-1)-Bit Squaring Circuit Architecture
2.2.1.1 Architecture for Case 1: A < B
2.2.1.2 Architecture for Case 2: A > B
2.2.1.3 Architecture for Case 3: A = B
2.3 Results and Discussion
2.4 Conclusion
References
3. Machine Learning–Based VLSI Test and VerificationJyoti Kandpal
3.1 Introduction
3.2 The VLSI Testing Process
3.2.1 Off-Chip Testing
3.2.2 On-Chip Testing
3.2.3 Combinational Circuit Testing
3.2.3.1 Fault Model
3.2.3.2 Path Sensitizing
3.2.4 Sequential Circuit Testing
3.2.4.1 Scan Path Test
3.2.4.2 Built-In-Self Test (BIST)
3.2.4.3 Boundary Scan Test (BST)
3.2.5 The Advantages of VLSI Testing
3.3 Machine Learning’s Advantages in VLSI Design
3.3.1 Ease in the Verification Process
3.3.2 Time-Saving
3.3.3 3Ps (Power, Performance, Price)
3.4 Electronic Design Automation (EDA)
3.4.1 System-Level Design
3.4.2 Logic Synthesis and Physical Design
3.4.3 Test, Diagnosis, and Validation
3.5 Verification
3.6 Challenges
3.7 Conclusion
References
4. IoT-Based Smart Home Security Alert System for Continuous SupervisionRajeswari, N. Vinod Kumar, K. M. Suresh, N. Sai Kumar and K. Girija Sravani
4.1 Introduction
4.2 Literature Survey
4.3 Results and Discussions
4.3.1 Raspberry Pi-3 B+Module
4.3.2 Pi Camera
4.3.3 Relay
4.3.4 Power Source
4.3.5 Sensors
4.3.5.1 IR & Ultrasonic Sensor
4.3.5.2 Gas Sensor
4.3.5.3 Fire Sensor
4.3.5.4 GSM Module
4.3.5.5 Buzzer
4.3.5.6 Cloud
4.3.5.7 Mobile
4.4 Conclusions
References
5. A Detailed Roadmap from Conventional-MOSFET to Nanowire-MOSFETP. Kiran Kumar, B. Balaji, M. Suman, P. Syam Sundar, E. Padmaja and K. Girija Sravani
5.1 Introduction
5.2 Scaling Challenges Beyond 100nm Node
5.3 Alternate Concepts in MOFSETs
5.4 Thin-Body Field-Effect Transistors
5.4.1 Single-Gate Ultrathin-Body Field-Effect Transistor
5.4.2 Multiple-Gate Ultrathin-Body Field-Effect Transistor
5.5 Fin-FET Devices
5.6 GAA Nanowire-MOSFETS
5.7 Conclusion
References
6. Gate All Around MOSFETs-A Futuristic ApproachRitu Yadav and Kiran Ahuja
6.1 Introduction
6.1.1 Semiconductor Technology: History
6.2 Importance of Scaling in CMOS Technology
6.2.1 Scaling Rules
6.2.2 The End of Planar Scaling
6.2.3 Enhance Power Efficiency
6.2.4 Scaling Challenges
6.2.4.1 Poly Silicon Depletion Effect
6.2.4.2 Quantum Effect
6.2.4.3 Gate Tunneling
6.2.5 Horizontal Scaling Challenges
6.2.5.1 Threshold Voltage Roll-Off
6.2.5.2 Drain Induce Barrier Lowering (DIBL)
6.2.5.3 Trap Charge Carrier
6.2.5.4 Mobility Degradation
6.3 Remedies of Scaling Challenges
6.3.1 By Channel Engineering (Horizontal)
6.3.1.1 Shallow S/D Junction
6.3.1.2 Multi-Material Gate
6.3.2 By Gate Engineering (Vertical)
6.3.2.1 High-K Dielectric
6.3.2.2 Metal Gate
6.3.2.3 Multiple Gate
6.4 Role of High-K in CMOS Miniaturization
6.5 Current Mosfet Technologies
6.6 Conclusion
References
7. Investigation of Diabetic Retinopathy Level Based on Convolution Neural Network Using Fundus ImagesK. Sasi Bhushan, U. Preethi, P. Naga Sai Navya, R. Abhilash, T. Pavan and K. Girija Sravani
7.1 Introduction
7.2 The Proposed Methodology
7.3 Dataset Description and Feature Extraction
7.3.1 Depiction of Datasets
7.3.2 Preprocessing
7.3.3 Detection of Blood Vessels
7.3.4 Microaneurysm Detection
7.4 Results and Discussions
7.5 Conclusions
References
8. Anti-Theft Technology of Museum Cultural Relics Using RFID TechnologyB. Ramesh Reddy, K. Bhargav Manikanta, P.V.V.N.S. Jaya Sai, R. Mohan Chandra, M. Greeshma Vyas and K. Girija Sravani
8.1 Introduction
8.2 Literature Survey
8.3 Software Implementation
8.4 Components
8.4.1 Arduino UNO
8.4.2 EM18 Reader Module
8.4.3 RFID Tag
8.4.4 LCD Display
8.4.5 Sensors
8.4.5.1 Fire Sensor
8.4.5.2 IR Sensor
8.4.6 Relay
8.5 Working Principle
8.5.1 Working Principle
8.6 Results and Discussions
8.7 Conclusions
References
9. Smart Irrigation System Using Machine Learning TechniquesB. V. Anil Sai Kumar, Suryavamsham Prem Kumar, Konduru Jaswanth, Kola Vishnu and Abhishek Kumar
9.1 Introduction
9.2 Hardware Module
9.2.1 Soil Moisture Sensor
9.2.2 LM35-Temperature Sensor
9.2.3 POT Resistor
9.2.4 BC-547 Transistor
9.2.5 Sounder
9.2.6 LCD 16x2
9.2.7 Relay
9.2.8 Push Button
9.2.9 LED
9.2.10 Motor
9.3 Software Module
9.3.1 Proteus Tool
9.3.2 Arduino Based Prototyping
9.4 Machine Learning (Ml) Into Irrigation
9.5 Conclusion
References
10. Design of Smart Wheelchair with Health Monitoring SystemNarendra Babu Alur, Kurapati Poorna Durga, Boddu Ganesh, Manda Devakaruna, Lakkimsetti Nandini, A. Praneetha, T. Satyanarayana and K. Girija Sravani
10.1 Introduction
10.2 Proposed Methodology
10.3 The Proposed System
10.4 Results and Discussions
10.5 Conclusions
References
11. Design and Analysis of Anti-Poaching Alert System for Red Sandalwood SafetyK. Rani Rudrama, Mounika Ramala, Poorna sasank Galaparti, Manikanta Chary Darla, Siva Sai Prasad Loya and K. Srinivasa Rao
11.1 Introduction
11.2 Various Existing Proposed Anti-Poaching Systems
11.3 System Framework and Construction
11.4 Results and Discussions
11.5 Conclusion and Future Scope
References
12. Tumor Detection Using Morphological Image Segmentation with DSP Processor TMS320C6748T. Anil Raju, K. Srihari Reddy, Sk. Arifulla Rabbani, G. Suresh, K. Saikumar Reddy and K. Girija Sravani
12.1 Introduction
12.2 Image Processing
12.2.1 Image Acquisition
12.2.2 Image Segmentation Method
12.3 TMS320C6748 DSP Processor
12.4 Code Composer Studio
12.5 Morphological Image Segmentation
12.5.1 Optimization
12.6 Results and Discussions
12.7 Conclusions
References
13. Design Challenges for Machine/Deep Learning AlgorithmsRajesh C. Dharmik and Bhushan U. Bawankar
13.1 Introduction
13.2 Design Challenges of Machine Learning
13.2.1 Data of Low Quality
13.2.2 Training Data Underfitting
13.2.3 Training Data Overfitting
13.2.4 Insufficient Training Data
13.2.5 Uncommon Training Data
13.2.6 Machine Learning Is a Time-Consuming Process
13.2.7 Unwanted Features
13.2.8 Implementation is Taking Longer Than Expected
13.2.9 Flaws When Data Grows
13.2.10 The Model’s Offline Learning and Deployment
13.2.11 Bad Recommendations
13.2.12 Abuse of Talent
13.2.13 Implementation
13.2.14 Assumption are Made in the Wrong Way
13.2.15 Infrastructure Deficiency
13.2.16 When Data Grows, Algorithms Become Obsolete
13.2.17 Skilled Resources are Not Available
13.2.18 Separation of Customers
13.2.19 Complexity
13.2.20 Results Take Time
13.2.21 Maintenance
13.2.22 Drift in Ideas
13.2.23 Bias in Data
13.2.24 Error Probability
13.2.25 Inability to Explain
13.3 Commonly Used Algorithms in Machine Learning
13.3.1 Algorithms for Supervised Learning
13.3.2 Algorithms for Unsupervised Learning
13.3.3 Algorithm for Reinforcement Learning
13.4 Applications of Machine Learning
13.4.1 Image Recognition
13.4.2 Speech Recognition
13.4.3 Traffic Prediction
13.4.4 Product Recommendations
13.4.5 Email Spam and Malware Filtering
13.5 Conclusion
References
About the Editors
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